The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures that include vertically-arranged field-effect transistors and methods for forming a structure that includes vertically-arranged field-effect transistors.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate associated with their formation. Planar field-effect transistors and fin-type field-effect transistors constitute a category of transistor structures in which the flow of gated current in the channel is oriented in a horizontal direction parallel to the substrate surface.